Insu Choi
Senior Research Engineer · Memory Systems Research
SK hynix
About me
I am a Senior Research Engineer in Memory Systems Research at SK hynix. I received my Ph.D. from Yonsei University, where I was advised by Professor Joon-Sung Yang. My Ph.D. research focused on LLM system optimization and AI accelerators, as well as memory reliability for fault-tolerant deep neural networks (DNNs).
Interests
- LLM System Optimization
- AI Accelerator
- Memory Reliability
Education
PhD in Electrical and Electronic Engineering, 2026
Yonsei University
BS in Electrical and Electronic Engineering, 2023
Yonsei University
Publications
(2026).
HiLLM: Heterogeneous CPU–GPU Inference for Interactive MoE LLM Serving on Local Systems.
2026 59th IEEE/ACM International Symposium on Microarchitecture (MICRO).
(2025).
DBC: Drift-aware Binary Code for Drift-tolerant Deep Neural Networks.
2025 62th ACM/IEEE Design Automation Conference (DAC).
(2025).
Bit-slice Architecture for DNN Acceleration with Slice-level Sparsity Enhancement and Exploitation.
2025 31st IEEE International Symposium on High-Performance Computer Architecture (HPCA).
(2024).
ViT-slice: End-to-end Vision Transformer Accelerator with Bit-slice Algorithm.
2024 61th ACM/IEEE Design Automation Conference (DAC).
(2023).
RQ-DNN: Reliable Quantization for Fault-tolerant Deep Neural Networks.
2023 60th ACM/IEEE Design Automation Conference (DAC) Late Breaking Results.
Skills
Technical
Python
C/C++
Verilog
Hobbies
Programming
Tennis
Games
Contact
- insuofficial@yonsei.ac.kr
- Room 411, Engineering Research Park, Yonsei University, 50 Yonsei-ro, Sinchon-dong, Seoul, South Korea 03722