Abstract
This paper proposes a novel memory architecture, PIE-DRAM, to mitigate the performance overhead caused by IECC. Unlike conventional IECC architectures, the proposed method separates IECC from data path to enable independent IECC operations from memory read or write access. Based on recent memory access histories, memory controller selectively determines the usage of IECC to alleviate IECC overhead, thereby the proposed architecture enhances the memory performance. Experimental results show that, from memory intensive workloads, 6% IPC (Instructions Per Cycle) improvement is achieved solely by applying the proposed DRAM architecture utilizing the locality and modified RMW.
Insu Choi
Ph.D. Student in AI / Computer Architecture
My research interests include AI/ML, AI accelerator and memory reliability.